The present invention relates generally to fabrication of field effect transistors having scaled-down dimensions, and more particularly, to a process for fabricating a transistor having a gate insulators which provide reduced leakage while improving carrier mobility by reducing scattering.
A long-recognized important objective in the constant advancement of monolithic integrated circuit (IC) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and aids in obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication by providing more die per semiconductor wafer. Such advantages are a driving force to constantly scale down IC dimensions.
Referring to FIG. 1, a common component of a monolithic IC is a MOS transistor 100 which is fabricated within or on a semiconductor substrate 102. The scaled down MOS transistor 100 having submicron or nanometer dimensions includes a drain extension region 104 and a source extension region 106 formed within an active device area 126 of the semiconductor substrate 102. The drain extension region 104 and the source extension region 106 are shallow junctions to minimize short-channel effects in the MOS transistor 100 having submicron or nanometer dimensions, as known to one of ordinary skill in the art of integrated circuit fabrication.
The transistor device 100 further includes a drain region 108 and a source region 112. The drain region 108 and the source region 112 are fabricated as deeper junctions such that a relatively large size of a drain silicide and source silicide (not shown), respectively, may be fabricated therein to provide a low resistance contact to the drain and the source, respectively. The drain and source extension junctions 104 and 106 and the drain and source regions 108 and 112 are doped with an N-type dopant for an NMOS (N-channel transistor) and with a P-type dopant for a PMOS (P-channel) device.
The transistor 100 further includes a gate dielectric 116 and a gate electrode 118 which may be polysilicon. A gate silicide (not shown) is formed typically on the polysilicon gate electrode 118 for providing contact to the gate of the device 100. The transistor 100 is electrically isolated from other integrated circuit devices within the semiconductor substrate 102 by, for example, shallow trench isolation structures 121. The shallow trench isolation structures 121 define the active device area 126 within the semiconductor substrate 102, where the MOSFET 100 is fabricated therein.
The device 100 also includes a spacer 122 disposed on the sidewalls of the gate electrode 118 and the gate dielectric 116. When the spacer 122 is comprised of silicon nitride (Si3N4), then a spacer liner oxide (not shown) may be deposited as a buffer layer between the spacer 122 and the sidewalls of the gate electrode 118 and the gate dielectric 116.
As the dimensions of the transistor 100 are scaled down to tens of nanometers, short-channel effects degrade the performance of the device 100. Short-channel effects that result due to the short length of the channel between the drain extension region 104 and the source extension region 106 are known to one of ordinary skill in the art of integrated circuit fabrication. The electrical characteristics of the transistor 100 become difficult to control with bias on the gate electrode 118 due to short-channel effects which may severely degrade the performance of the MOS device.
Conventionally, the gate dielectric 116 for the MOSFET 100 is typically silicon dioxide (SiO2), and the gate electrode 118 is typically comprised polysilicon. As the channel length and width dimensions of the transistor 100 are scaled down for enhanced speed performance, the thicknesses of the gate dielectric 116 and the gate electrode 118 are also correspondingly scaled down, as known to one of ordinary skill in the art of integrated circuit fabrication. However, as the channel length and width dimensions of the device 100 are scaled down to tens of nanometers, the thickness of the gate dielectric 116 is also scaled down to tens of angstroms when the gate dielectric 116 is silicon dioxide (SiO2). With such a thin gate dielectric 116, charge carriers in some cases easily tunnel through the gate dielectric 116, as known to one of ordinary skill in the art of integrated circuit fabrication.
When charge carriers tunnel through the gate dielectric 116, gate leakage current undesirably increases, resulting in increased static power dissipation and even circuit malfunction. In addition, with charge carriers tunneling through the gate dielectric 116, decreased charge carrier accumulation in the channel of the transistor may result in an undesirable increase in MOSFET channel resistance. Furthermore, with the thin gate dielectric 116, charge accumulation at the gate electrode 118 causes an undesirable increase in charge carrier scattering at the surface of the channel of the device. Such increase in charge carrier scattering in turn results in higher resistance through the channel of the MOSFET and reduced carrier mobility.
In light of the disadvantages of the thin gate dielectric 116 when the gate dielectric 116 is silicon dioxide (SiO2), referring to FIG. 2, a MOS transistor 150 is shown which has a gate dielectric 152 comprised of a dielectric material having a dielectric constant that is higher than the dielectric constant of silicon dioxide (SiO2) (i.e., a high-k dielectric constant material). Device structures having the same reference number in FIGS. 1 and 2 refer to elements having similar structure and function. A dielectric material having a higher dielectric constant has higher thickness for achieving the same capacitance. Thus, when the gate dielectric 152 is comprised of a high-k dielectric constant material, the gate dielectric 152 has a larger thickness (hundreds of angstroms) than when the gate dielectric is comprised of silicon dioxide (SiO2) (tens of angstroms), for field effect transistors having scaled down dimensions of tens of nanometers.
The gate dielectric 152 with a high-k dielectric constant has larger thickness to minimize charge carrier tunneling through the gate dielectric 152 for field effect transistors having scaled down dimensions of tens of nanometers. Charge carrier tunneling through the gate dielectric 152 is minimized exponentially by the thickness of the gate dielectric. Dielectric materials having a dielectric constant that is higher than the dielectric constant of silicon dioxide (SiO2) are known to one of ordinary skill in the art of integrated circuit fabrication.
Although high-k dielectric materials used as gate insulators do act to reduce gate leakage, such materials tend to disadvantageously reduce carrier mobility which negatively impacts transistor speed. Therefore there is a need in the art for further improvements in transistor structure and methods of manufacture.
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended neither to identify key or critical elements of the invention nor to delineate the scope of the invention. Its primary purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later. The present invention relates to an improved MOS transistor which exhibits reduced remote scattering in advanced gate insulator device structures.
In accordance with one aspect of the present invention, a MOS transistor is disclosed in which a source and drain region reside in a silicon substrate having a channel region therebetween. A gate insulator resides over the channel region, and the gate insulator comprises a high-k dielectric layer interposed between two thin silicon dioxide layers such as monolayers. A doped polysilicon gate overlies the gate insulator. The thin silicon dioxide layers surrounding the top and bottom surfaces of the high-k dielectric layer provide for a quality interface between the gate insulator and the silicon substrate and the gate insulator and doped polysilicon gate, respectively. The quality interface allows the high-k dielectric layer to improve transistor performance by decreasing gate leakage current without adversely impacting transistor carrier mobility.
In accordance with another aspect of the invention, the MOS transistor comprises a doped polysilicon gate which comprises an interface portion which directly overlies the above gate insulator, and a gate electrode portion that overlies the interface portion. The interface portion and the gate electrode portion of the doped polysilicon gate have different thicknesses and different dopant concentrations. In particular, the interface portion is substantially thinner than the gate electrode portion and has a dopant concentration that is about six or more times less than the gate electrode portion. The customized poly gate doping of the interface portion of the doped polysilicon gate provides improved carrier mobility with little negative impact of poly gate depletion and therefore serves to improve transistor performance over the prior art.
In accordance with yet another aspect of the present invention, a method of forming a MOS transistor having improved carrier mobility is provided. The method comprises forming a gate insulator over a silicon substrate, wherein the gate insulator comprises a high-k dielectric material interposed between the two thin silicon dioxide layers such as monolayers. The thin silicon dioxide layers are formed, for example, using molecular beam epitaxy (MBE) or atomic layer epitaxy (ALE) while the high-k dielectric is formed, for example, by chemical vapor deposition (CVD) or reactive sputtering. A doped polysilicon layer is then formed and patterned to define a gate electrode. Source and drain regions are formed in the silicon substrate, for example, by ion implantation using the poly gate as a mask.
In accordance with another aspect of the present invention, the above method further comprises forming the doped polysilicon layer by separating the formation thereof into two portions. A first polysilicon layer (for example, an interface portion) is formed in contact with the gate insulator with a first dopant concentration and a second polysilicon layer (for example, a gate electrode portion) is formed thereover having a second dopant concentration which is substantially greater than the first dopant concentration. For example, a first polysilicon layer may be deposited and doped in-situ with the first dopant concentration followed by a second poly layer deposition with in-situ doping with the second, greater dopant concentration. Alternatively, a single polysilicon layer is deposited, followed by a first doping at a first energy level and a second doping at a second, lesser energy level. In the above manner, upon activation, a custom poly doping profile is established in the poly gate which reduces carrier mobility degradation due to scattering.
In accordance with still another aspect of the present invention, another MOS transistor is disclosed. The MOS transistor comprises a source and drain region in a silicon substrate having a channel region therebetween. A gate insulator resides over the channel region, and comprises a thin silicon dioxide layer such as a monolayer overlying the silicon substrate and a high-k dielectric layer formed thereover. A high-k metal gate electrode resides over the high-k dielectric, wherein the high-k metal material corresponds to the high-k dielectric material. For example, the high-k dielectric may comprise HfO2 while the high-k metal gate comprises Hf, or the high-k dielectric may comprise Ta2O5 while the high-k metal gate comprises Ta, respectively. By employing the thin SiO2 layer, a quality interface exists between the substrate and the gate insulator which reduces remote scattering, and thereby improves carrier mobility. In addition, by having the high-k dielectric layer material correspond to the high-k metal material, a quality material interface resides at the gate insulator/gate electrode interface, thereby further improving carrier mobility.
In accordance with yet another aspect of the present invention, a method of forming the MOS transistor above having improved carrier mobility is provided. The method comprises forming a gate insulator over a silicon substrate, wherein the gate insulator comprises a high-k dielectric material overlying a thin silicon dioxide layer such as a monolayer. The thin silicon dioxide layer is formed, for example, using molecular beam epitaxy (MBE) or atomic layer epitaxy (ALE) while the high-k dielectric is formed, for example, by chemical vapor deposition (CVD) or reactive sputtering. A high-k metal layer is then formed over the high-k dielectric layer, wherein the high-k metal material corresponds to the high-k dielectric material, thereby providing a high quality interface between the gate insulator and the metal gate electrode.
In one exemplary aspect of the present invention, the high-k dielectric material is formed via reactive sputtering, followed by a sputtering process in the same chamber, wherein an oxygen content in the environment associated therewith is substantially reduced, thereby facilitating a process where no interfacial layers form at the gate insulator/gate electrode interface.